1. Field of the Invention
The present invention generally relates to an offset cancel circuit of a voltage follower equipped with an operational amplifier, and more specifically to a voltage follower suitably applied to the output stage of a data driver for a liquid crystal display device that frequently carries out the offset cancel, an offset cancel circuit thereof, and a data driver, for a liquid crystal display device, employing the voltage follower in the output stage thereof.
2. Description of the Related Art
FIG. 8 is a circuit diagram showing a prior art voltage follower with offset-cancel disclosed in JP 2001-292041-A.
An operational amplifier 10 comprises a differential amplifying circuit 11 and an output buffer circuit 12 connected to a subsequent stage thereof, and is used as a voltage follower whose amplification factor is 1, by feeding back the output potential VO of the output buffer circuit 12 to the gate of an NMOS transistor M1 as an inverting input of the differential amplifying circuit 11. The input potential VI of the voltage follower is provided to the gate of an NMOS transistor M2 as a non-inverting input. In an ideal case, the relation of VO=VI holds by the feedback control, with the drain potentials V1 and V2 of PMOS transistors M4 and M5 as the loads of the differential amplifying circuit 11 being equal to each other.
However, the potentials V1 and V2 become not equal to each other due to variations in the thickness of the gate oxide layer of MOS transistor, causing an offset in which the output potential VO differs from the input potential VI.
In order to cancel the offset, an offset cancel circuit 13 is connected to the operational amplifier 10.
FIG. 9 is a time chart showing the operation of the circuit of FIG. 8.
During an offset cancel preparation period from a time t1 to a time t2, switches SW1 and SW3 are on, while a switch SW2 is off. Thereby, the output potential VO is not fed back to the gate of the NMOS transistor M1, and both the gate potentials of the NMOS transistors M1 and M2 are equal to the input potential V1. Therefore, the differential input circuit 15 operates as a current source for the current mirror circuit 14.
On the other hand, the input potential V1 is provided to the gate of an NMOS transistor M9, and the output potential VO is fed back to the gate of an NMOS transistor M8. Therefore, a voltage follower circuit is configured with the output buffer circuit 12 and a differential amplifying circuit that includes the current mirror circuit 14 and a differential input circuit 16, and thereby the output potential VO is feedback-controlled so as to become close to the input potential VI.
In this case, when, for example, “V1>V2” is also caused because of the above-mentioned reason, the internal resistance of the PMOS transistor M6 becomes lower than that of the ideal case, causing the output potential VO to be larger than the input potential VI. This causes the drain current of the NMOS transistor M8 to be larger than that of the NMOS transistor M9. A capacitor C1 is charged or discharged with the output potential VO, and the potential of its one electrode on the switch SW3 side becomes equal to the output potential VO.
The switches SW1 to SW3 are turned over at the time t2, whereby the operations of the differential input circuits 15 and 16 change over to each other, a voltage follower is configured with the differential amplifying circuit 11 and the output buffer circuit 12, and the output potential VO is feedback-controlled so as to become close to the input potential VI. Here, because the gate potential of the NMOS transistor M8 is equal to the output potential VO at the time t2, the gate potential of the NMOS transistor M1 is feedback-controlled to be equal to the input potential VI. Namely, VO=VI is achieved, canceling the offset voltage.
In a case where the circuit of FIG. 8 is employed for a data driver of a liquid crystal display device, the input potential VI varies in a cycle of one horizontal scan period, for example, 22 μs.
The input potential VI depends on the display data, and there is a case where it changes from the minimum value to the maximum value or from the maximum value to the minimum value. In design, taking into consideration this worst case, a feedback-control time required to stabilize the output potential VO must be secured as an offset cancel preparation time. For this reason, as the number of display lines of a liquid crystal display device becomes larger, the time (driving time) to charge and discharge the capacitances of liquid crystal pixels with the output potential VO becomes shorter, leading to failure in driving of the pixels.